A resonance type converter is known as a switching power supply device for various kinds of electronic instrument. The resonance type converter is configured by a primary coil of an insulating transformer being connected via a capacitor to a direct current voltage supply. A series resonant circuit is formed of a leakage inductor of the insulating transformer and the capacitor. The resonance type converter controls resonance current flowing through the series resonant circuit using first and second switching elements driven on and off in a complementary way, obtaining stepped-up or stepped-down direct current voltage from a secondary coil side of the insulating transformer.
For example, soft switching technology for this kind of switching power supply device is proposed in PTL 1 and 2. The soft switching technology is such that loss in the switching elements is considerably reduced by the switching elements being turned off when the voltage applied to each of the switching elements is zero (0), or when the current flowing through the inductor is zero (0).
This resonance type switching power supply device 1, in outline, is such that a primary coil P1 of an insulating transformer T is connected via a capacitor C to a direct current voltage supply B, and includes a series resonant circuit formed of a leakage inductor of the insulating transformer T and the capacitor C, as shown in, for example, FIG. 12. A first switching element Q1 connected in series to the primary coil P1 of the insulating transformer T is driven on by a drive control circuit A that carries out a separately-excited oscillation operation, and applies an input voltage Vin from the direct current voltage supply B to the series resonant circuit. The drive control circuit A is formed of, for example, a power supply IC. Also, a second switching element Q2 connected in parallel to the series resonant circuit is driven on by the drive control circuit A when the first switching element Q1 is in an off-state, thus forming a resonance current path of the series resonant circuit. The first and second switching elements Q1 and Q2 are formed of, for example, high breakdown voltage n-type MOSFETs.
Power generated in secondary coils S1 and S2 of the insulating transformer T is rectified and smoothed via an output circuit formed of diodes D1 and D2 and an output capacitor Cout, and supplied as an output voltage Vout to an unshown load. A resonance type power conversion device main body is structured of these circuit portions. Further, the output voltage Vout, specifically the deviation between the output voltage Vout and an output voltage setting value, is detected by an output voltage detector circuit Vos, and fed back as an FB voltage to the drive control circuit A via a photocoupler PC.
The FB voltage fed back to the drive control circuit A is used in pulse width modulation of output control signals that drive the first and second switching elements Q1 and Q2 on and off, whereby the output voltage Vout is stabilized. Direct current power supplied from the direct current voltage supply B is generally filtered via an input capacitor Cin, and subsequently fed as the input voltage Vin to the switching power supply device.
Herein, the drive control circuit A is configured mainly of an output control circuit 2, a dead time circuit 3, and a drive signal generator circuit 4, as in a schematic configuration thereof shown in, for example, FIG. 13. Furthermore, the drive control circuit A includes a drive amplifier 5 as a drive circuit that drives the first switching element Q1 and a drive circuit 6 as a drive circuit that drives the second switching element Q2. In FIG. 13, 7 is a level shifter circuit for shifting the level of a drive signal generated by the drive signal generator circuit 4, and inputting the drive signal into the drive circuit 6. Also, 8 is an internal power supply circuit that generates voltage VDD necessary for operations of the output control circuit 2, the dead time circuit 3, and the drive signal generator circuit 4 from a drive voltage VCC applied to the drive control circuit A.
The output control circuit 2, for example, generates a PWM signal having a pulse width in accordance with the FB voltage fed back from the output voltage detector circuit Vos as an output control signal CO. The on-state periods of the first and second switching elements Q1 and Q2 are prescribed by the output control signal CO, and the output voltage Vout accompanying switching operations of the switching elements Q1 and Q2 is controlled so as to be of the output voltage setting value. The output control circuit 2 may also be such as to generate a PFM signal having a frequency in accordance with the FB voltage as the output control signal CO, instead of the PWM signal.
The dead time circuit 3 includes a charge/discharge capacitor 3c, charged by a constant current supply 3b via a charge switch 3a, and a discharge switch 3d that discharges a charge accumulated in the charge/discharge capacitor 3c, for example, as shown in FIG. 14. The charge switch 3a and discharge switch 3d are formed of, for example, a p-type MOSFET and an n-type MOSFET. The charge switch 3a and discharge switch 3d are controlled so as to be turned on and off in a complementary way by the output control signal CO output from the output control circuit 2.
Furthermore, the dead time circuit 3 includes a comparator 3e that compares a charge/discharge voltage Vcd of the charge/discharge capacitor 3c with a preset threshold value voltage Vdt, and inverts when the charge/discharge voltage Vcd exceeds the threshold value voltage Vdt. Further, by a logical operation being carried out on the output of the comparator 3e and the output control signal CO in a NOR circuit 3f, a dead time signal DT of a constant pulse width Tdt is generated. The dead time signal DT is a timing adjustment signal for turning on the switching elements Q1 and Q2 when the voltage applied to the first and second switching elements Q1 and Q2 is zero (0).
Meanwhile, the drive signal generator circuit 4 and level shifter circuit 7 are configured as shown in, for example, FIG. 15. That is, the drive signal generator circuit 4 is formed of a logic circuit that generates pulse width controlled drive signals DH and DL, which drive on the first and second switching elements Q1 and Q2 respectively, in accordance with the dead time signal DT and output control signal CO. Specifically, the drive signal generator circuit 4 is such that a logical operation is carried out on the output control signal CO and dead time signal DT in a NOR circuit 4a, whereby the low side drive signal DL for driving the first switching element Q1 is generated. Also, the drive signal generator circuit 4 is such that, at the same time, a logical operation is carried out on the dead time signal DT, inverted via an inverter circuit 4b, and the output control signal CO in an AND circuit 4c, whereby the high side drive signal DH for driving the second switching element Q2 is generated.
Herein, the second switching element Q2 carries out a switching operation under a condition of a high voltage being applied to the primary coil P1 of the insulating transformer T. Also, the drive circuit 6 is configured so as to operate between a high voltage VB applied to the primary coil P1 and an operating reference voltage VS of the second switching element Q2, as shown in FIG. 13, in accordance with the operating voltage of the second switching element Q2. As opposed to this, the drive signal generator circuit 4 is configured so as to operate, for example, between the operating reference voltage VS and a ground potential. Therefore, the level shifter circuit 7 performs a role of shifting the level of the drive signal DH output by the drive signal generator circuit 4 to coincide with the operating reference voltage VS of the drive circuit 6.
The level shifter circuit 7, in outline, includes level shifting first and second transistors 7c and 7d formed of n-type MOSFETs whose drains are connected via load resistors 7a and 7b to the high voltage VB. Also, the level shifter circuit 7 includes a first rising edge trigger circuit 7e, which outputs a pulse signal PS at the timing at which the drive signal DH rises, and a second rising edge trigger circuit 7g which, by the drive signal DH being inverted via an inverter circuit 7f, outputs a pulse signal PE at the timing at which the drive signal DH falls.
The first and second rising edge trigger circuits 7e and 7g drive the transistors 7c and 7d respectively using the pulse signals PS and PE, which are the outputs of the first and second rising edge trigger circuits 7e and 7g. As a result of this, pulse signals PShigh and PEhigh, synchronized with the timings of the rise and fall respectively of the drive signal DH and level-shifted to a high potential, are obtained as drain voltages of the transistors 7c and 7d respectively, as shown in FIG. 16. By the output circuit 7h, which structures a flip-flop, being set and reset by the pulse signals PShigh and PEhigh, the drive signal DH is level-shifted and reproduced as the output of the output circuit 7h. In this way, the level-shifted drive signal DH is applied to the drive circuit 6, whereby the second switching element Q2 is driven on and off. 7i and 7j in FIG. 15 are recovery diodes connected in anti-parallel to the load resistors 7a and 7b. 
Herein, a simple description will be given of an operation of a resonance type converter, which is the switching power supply device with the heretofore described configuration. The resonance type converter is such that, by the first switching element Q1 being turned on when the second switching element Q2 is in an off-state, current flows through the series resonant circuit. When the first switching element Q1 is turned off in this state, an unshown parasitic capacitor of the first switching element Q1 is charged by current flowing through an inductor of the series resonant circuit. At the same time, an unshown parasitic capacitor of the second switching element Q2 is discharged by the current.
Further, by the second switching element Q2 being turned on when the charge voltage of the parasitic capacitor of the first switching element Q1 reaches the input voltage Vin, zero voltage switching of the second switching element Q2 is realized. In accompaniment to the second switching element Q2 being turned on, electric power energy stored in the capacitor C now flows via the second switching element Q2. Consequently, the current flowing through the inductor of the series resonant circuit is inverted.
When the second switching element Q2 is subsequently turned off, the parasitic capacitor of the second switching element Q2 is now charged by the current inverted as previously described. At the same time, the parasitic capacitor of the first switching element Q1 is discharged by the current. Further, by the first switching element Q1 being turned on when the charge voltage of the parasitic capacitor of the second switching element Q2 reaches zero (0) voltage, zero voltage switching of the first switching element Q1 is realized. By the first switching element Q1 being turned on, the current of the series resonant circuit is inverted, and flows via the first switching element Q1 again. The previously described dead time signal, with the timing at which one of these kinds of first and second switching elements Q1 and Q2 is turned off as a reference, is used for prescribing the timing at which the other of the switching elements Q1 and Q2 is turned on. cl CITATION LIST